ESP32使用Flash Encryption不成功的原因？

ti

您好, 我在ESP32S3上使用Flash Encryption成功，但是在ESP32上使用不成功，问题如下

使用流程：
1. 产生固定的key.bin档案
2. 将key.bin写进装置
  espefuse.py -p com20 burn_key BLOCK1 esp32_key1.bin --no-protect-key
3. 烧录Efuse，burn_efuse FLASH_CRYPT_CNT 1、FLASH_CRYPT_CONFIG 0xF
4. 使用以下指令加密档案
  espsecure.py encrypt_flash_data --flash_crypt_conf 0xf --keyfile esp32_key1.bin --address 0x10000 --output app2.ebin GetChipID.ino.bin
5. 烧录加密的档案

问题如下：
1. 我使用 --no-protect-key 写入 key.bin档案，发现读回的 key 值，不同于威廉希尔官方网站文件中，数值的顺序相反，我有2台ESP32，使用相同的key.bin 但读回的 key值皆不同，如附件

2. 要如何加密档案，使其能够与--encrypt加密的档案相同呢？除了使用相同的key.bin、--flash_crypt_conf 0xf，加上 --aes_xts 也是不同，是否还有其他需要注意的地方？

验证方式
使用 --encrypt 写入各档案，再使用 esptool.py read_flash 读回档案，发现与自行加密的档案不同

目前的 Efuse summary

espefuse.py v3.3.2
Connecting...
Failed to get PID of a device on com20, using standard reset sequence.
..
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting...
Failed to get PID of a device on com20, using standard reset sequence.
....
Detecting chip type... ESP32

=== Run "summary" command ===
EFUSE_NAME (Block) Description  = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0):                      BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0):                               Voltage reference calibration                   = 1100 R/W (0b10000)

Config fuses:
XPD_SDIO_FORCE (BLOCK0):                         Ignore MTDI pin (GPIO12) for VDD_SDIO on reset    = False R/W (0b0)
XPD_SDIO_REG (BLOCK0):                            If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0):                         If XPD_SDIO_FORCE XPD_SDIO_REG                = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0):                            8MHz clock freq override                         = 51 R/W (0x33)
SPI_PAD_CONFIG_CLK (BLOCK0):                      Override SD_CLK pad (GPIO6/SPICLK)                = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0):                      Override SD_DATA_0 pad (GPIO7/SPIQ)             = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0):                      Override SD_DATA_1 pad (GPIO8/SPID)             = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0):                      Override SD_DATA_2 pad (GPIO9/SPIHD)             = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0):                      Override SD_CMD pad (GPIO11/SPICS0)             = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0):                      Disable SDIO host                               = False R/W (0b0)

Efuse fuses:
WR_DIS (BLOCK0):                                  Efuse write disable mask                         = 0 R/W (0x0000)
RD_DIS (BLOCK0):                                  Efuse read disable mask                         = 0 R/W (0x0)
CODING_SCHEME (BLOCK0):                         Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0):                            Usage of efuse block 3 (reserved)                = False R/W (0b0)

Identity fuses:
MAC (BLOCK0):                                     Factory MAC Address
= c8:f0:9e:0a:03:a8 (CRC 0x3e OK) R/W
MAC_CRC (BLOCK0):                               CRC8 for factory MAC address                      = 62 R/W (0x3e)
CHIP_VER_REV1 (BLOCK0):                         Silicon Revision 1                               = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0):                         Silicon Revision 2                               = True R/W (0b1)
CHIP_VERSION (BLOCK0):                            Reserved for future chip versions                = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0):                            Chip package identifier                         = 1 R/W (0b001)
CHIP_PACKAGE_4BIT (BLOCK0):                      Chip package identifier #4bit                   = False R/W (0b0)
MAC_VERSION (BLOCK3):                            Version of the MAC field                         = 0 R/W (0x00)

Security fuses:
FLASH_CRYPT_CNT (BLOCK0):                         Flash encryption mode counter                   = 1 R/W (0b0000001)
UART_DOWNLOAD_DIS (BLOCK0):                      Disable UART download mode (ESP32 rev3 only)    = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0):                      Flash encryption config (key tweak bits)          = 15 R/W (0xf)
CONSOLE_DEBUG_DISABLE (BLOCK0):                   Disable ROM BASIC interpreter fallback          = True R/W (0b1)
ABS_DONE_0 (BLOCK0):                            Secure boot V1 is enabled for bootloader image    = False R/W (0b0)
ABS_DONE_1 (BLOCK0):                            Secure boot V2 is enabled for bootloader image    = False R/W (0b0)
JTAG_DISABLE (BLOCK0):                            Disable JTAG                                     = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0):                      Disable flash encryption in UART bootloader       = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0):                      Disable flash decryption in UART bootloader       = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0):                      Disable flash cache in UART bootloader          = False R/W (0b0)
BLOCK1 (BLOCK1):                                  Flash encryption key
= 35 44 30 31 35 41 30 30 35 42 30 33 35 38 30 34 35 46 30 31 35 42 37 37 32 43 37 34 32 46 37 37 R/W
BLOCK2 (BLOCK2):                                  Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3):                                  Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
                                                                                                                                             Attachments

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