夏宇闻老师书第17章一个例子仿真的问题

代码如下：

module top(data,addr,ena,read,write);
inout [7:0] data;
input [9:0] addr;

input ena;
input read,write;

reg [7:0]  ram[6'h3f:0];


assign data=(read&&ena) ? ram[addr]:8'hzz;

always @(posedge write)
	begin	
		ram[addr]=data;
	end
endmodule

仿真代码如下：

`timescale 1 ns/ 1 ps
module top_vlg_tst();
// constants                                           
// general purpose registers
//reg eachvec;
// test vector input registers
reg [9:0] addr;
reg [7:0] ram[6'h3f:0];
reg ena;
reg read;
reg write;
// wires                                               
wire [7:0]  data;

// assign statements (if any)                          
assign data = (read && ena) ? ram[addr]:8'bzz;
top i1 (
// port map - connection between master ports and signals/registers   
	.addr(addr),
	.data(data),
	.ena(ena),
	.read(read),
	.write(write)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
  write=0;
	forever
		#5 write = ~write;
// --> end                                             
               
end                                                    
initial	
	begin
	  #10 begin addr=10'h3f;read=0;ena=0;ram[addr]=8'h55; end
	  #10 begin read=0;ena=1;ram[addr]=8'h55;end
	  #10 begin read=1;ena=0;ram[addr]=8'h55;end
	  #10 begin read=1;ena=1;ram[addr]=8'h55;end
	  #10 begin addr=10'h3e;read=1;ena=1;ram[addr]=8'haa;end
	  #10 begin addr=10'h3d;read=1;ena=1;ram[addr]=8'h5a;end
	  #10 begin addr=10'h3c;read=1;ena=1;ram[addr]=8'ha5;end
	  #20 $stop;
	 end
endmodule

仿真图形的一部分：

这是怎么回事？好像只读了一次，data就不更新了。然后就一直高阻。

请高手指教，谢谢！